1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising highly capacitive gate structures on the basis of a high-k dielectric material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that represent an interface formed by highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. It turns out that decreasing the channel length requires an increased capacitive coupling between the gate electrode and the channel region to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide based dielectrics, at least in part, as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would otherwise be obtained by an extremely thin silicon dioxide layer.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, at least in the vicinity of the gate dielectric material, since polysilicon may suffer from charge carrier depletion near the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, while maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone and providing superior conductivity compared to the doped polysilicon material. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration and the performance characteristics thereof has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the geometry of the gate electrode structures and of the resulting work function and thus threshold voltage of the completed transistor structures. Moreover, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. In other approaches, appropriate work function metals may be diffused into the gate dielectric material prior to actually patterning the gate electrode structures, thereby placing dipole charges in the gate dielectric material as required for adjusting the desired work function for the different transistors types. Hence, during the further processing, a pronounced temperature dependency may require a strict control of the thermal budget, which in turn may contribute to an increased variability of the transistor characteristics. Furthermore, frequently, the channel region of one type of transistor may require a band gap offset compared to a pure silicon channel in order to obtain a desired work function on the basis of a specific work function metal, such as aluminum for P-channel transistors, wherein, however, the adjustment of the band gap offset is typically accomplished by epitaxially forming a semiconductor material, such as a silicon/germanium mixture in the channel region, which in turn necessitates well-controlled processes that may reduce overall throughput.
For these reasons, in other approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and at least the deposition of the actual electrode metal and the final adjustment of the work function of the transistors are accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure. In a corresponding replacement gate approach, the high-k dielectric material may be formed and covered by an appropriate metal-containing material, such as titanium nitride and the like, followed by a standard polysilicon or amorphous silicon material, which may then be patterned on the basis of well-established advanced lithography and etch techniques. Consequently, during the process sequence for patterning the gate electrode structure, the sensitive high-k dielectric material may be protected by the metal-containing material, possibly in combination with sophisticated sidewall spacer structures, thereby substantially avoiding any undue material modification during the further processing. After patterning the gate electrode structure, conventional and well-established process techniques for forming the drain and source regions having the desired complex dopant profile are typically performed. After any high temperature processes, the further processing is continued, for instance by forming a metal silicide, if required, followed by the deposition of an interlayer dielectric material, such as silicon nitride in combination with silicon dioxide and the like. In this manufacturing stage, a top surface of the gate electrode structures embedded in the interlayer dielectric material is exposed, for instance by chemical mechanical polishing (CMP) and the like. The polysilicon material is removed in a selective etch process and, thereafter, an appropriate masking regime is applied in order to selectively fill in an appropriate work function metal for each type of transistor, which may be accomplished by filling in the first metal species and selectively removing the metal species from one of the gate electrode structures. Thereafter, a further metal material is deposited, thereby obtaining the desired work function for each type of transistor. Finally, the gate electrodes are filled with an electrode metal, thereby providing a full metal gate electrode structure for N-channel and P-channel transistors.
Although, in general, this approach may provide advantages in view of reducing process-related non-uniformities in the threshold voltages of the transistors since the high-k dielectric material may be reliably encapsulated during the entire process sequence without requiring an adjustment of the work function and thus the threshold voltage at an early manufacturing stage, the complex process sequence for removing the placeholder material and providing appropriate work function materials for the different types of transistors may also result in a significant degree of variability of the transistor characteristics, which may thus result in offsetting at least some of the advantages obtained by the common processing of the gate electrode structures until the basic transistor configuration is completed.
In other words, upon continuously shrinking the feature sizes and, thus, the gate length of the transistors, forming the gate openings or trenches formed upon removing the placeholder polysilicon material in the advanced manufacturing stage requires very sophisticated deposition techniques for depositing the first work function metal and depositing the second work function metal after removing the first work function metal from one of the gate trenches. Subsequently, the actual electrode material is to be filled in the gate trenches. Consequently, any deposition-related irregularities, such as voids and seams, for instance created in the actual electrode metal, may result in significant variations of electrical performance of the gate electrode structures. Furthermore, upon applying sophisticated deposition techniques for filling in the work function metals, for instance by establishing deposition conditions, in which preferably deposition may occur at the bottom of the gate trenches compared to the sidewall surface areas, any variations in thickness may, thus, result in significant threshold voltage variations. Moreover, upon applying any such sophisticated deposition techniques, it may be very difficult to appropriately adjust the work function values by depositing a desired specific thickness at the bottom of a gate trench under consideration. Generally, reducing the thickness of the work function metal so as to provide superior deposition conditions may, thus, not be a promising option in view of obtaining the desired work function of the gate electrode structures. Consequently, upon further device scaling, the deposition-related variations of transistor characteristics may increase in conventional replacement gate approaches.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.